1. Field of the Invention
The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods.
2. Background of the Invention
Methods of fabricating electronic components, such as nanowires and transistors, have historically been performed using metal-catalyzed vapor-liquid-solid (VLS) growth techniques, followed by subsequent device fabrication, for example, on a second substrate. The VLS approach, however, limits the types of devices that can be fabricated. For example, it is difficult to pattern gate or other electrodes on the VLS growth wafer as the structures are typically in a vertical orientation. In addition, it is difficult to create self-aligned source and drain doped structures, which are standard features of conventional metal oxide semiconductor (MOS) transistors. It is also challenging to create structures with lightly doped drain regions using traditional VLS techniques. In general, the vertical orientation of VLS-produced structures (e.g., nanowires) precludes many of the standard patterning techniques that are widely used in the semiconductor industry.
Furthermore, VLS growth utilizes metal catalysis, which often leads to contamination of the formed structures and does not allow for precise control of dimensions or surface smoothness.
What is needed therefore are methods for the production of substrate elements that overcome these deficiencies.